Field of the invention
This invention relates to Non-Volatile Static Random Access Memory (NVSRAM) and the methods of operations. In particular, only one single non-volatile element embedded in a conventional SRAM cell forms an NVSRAM cell device of the invention. A plurality of NVSRAM cell devices of the invention can be integrated into a compact memory array. Due to a new configuration of the NVSRAM device of the invention, switching elements in the conventional NVSRAM devices to isolate the SRAM cell from the high voltages of writing and erase operations of the non-volatile element are omitted. The operations of the NVSRAM cells of the invention are also simplified. The NVSRAM device of the invention has a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell.
Description of the Related Art
Semiconductor memories have been broadly applied to electronic systems. Electronic systems require semiconductor memories for storing instructions and datum from the basic functions of controls to the complex computing processes. Semiconductor memories can be catalogued as volatile memories and non-volatile memories. The volatile memories including Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) lose their stored datum after the memory's powers are turned off while the non-volatile memories such as Read Only Memory (ROM), Electrical Erasable Programmable Read Only Memory (EEPROM) and flash still keep their stored datum even without the memory power.
In one area of electronic system applications, the combination of volatile memories and non-volatile memories becomes particularly important for situations of power interruption or power failure. For examples, data logging for transactions and server data storages, printers, medical equipments, and vehicle crash recorders are the major fields of applications. The solutions for those applications have been evolving from SRAM in conjunction with controller and battery, SRAM in conjunction with battery, to NVSRAM in conjunction with discharging capacitors. Nowadays, the solution of NVSRAM in conjunction with discharging capacitors is the most compact and integrated system for the applications.
In early development stage of semiconductor NVSRAM, non-volatile elements (such as EEPROM or flash) are formed in one cell array to a one-to-one image of one SRAM cell array. In the situation of losing power, a built-in power detection circuitry in a conventional NVSRAM device detects the power dropping and begins to move the SRAM datum to the non-volatile elements using the power of the discharging capacitors or backup batteries. Since the non-volatile elements are separated from the SRAM array, the high voltages for Non-Volatile Memory (NVM) write/erase operations do not reach the low voltage circuitry of the SRAM operations. SRAM array is used as the data buffers for non-volatile memory programming. However, this approach is less compact and less efficient due to the two separated non-volatile memory array and SRAM array with peripheral circuitries.
To combine non-volatile element and SRAM cell for forming a single NVMSRAM cell is always the goal for compactness, better operational speed performance, and cost reduction. Several NVSRAM unit cell approaches, for examples, U.S. Pat. Nos. 6,556,487, 7,164,608, 7,110,293, 7,307,872, and 7,663,917, have been proposed. Although those single-unit-cell approaches have improved the compactness, operational speed performance, and cost reduction most of the NVSRAM cells would require multiple switches to isolate the SRAM cell portion from the non-volatile element in the NVSRAM unit cell. This is due to the incompatibility of high/low voltage operations of volatile and non-volatile cell devices. Some of the approaches also require two non-volatile elements for pulling up and down the SRAM cell bitline and complementary bitline. In terms, those approaches increase the numbers of transistor elements and add more operational complexity. As in U.S. Pat. No. 6,556,487, Ratnadumar et al. apply one single non-volatile element embedded in a 6T SRAM cell 110 as shown in FIG. 1 (FIG. 4 in U.S. Pat. No. 6,55,6487). In the NVSRAM cell configuration 100 of FIG. 1, the source and drain electrodes of the non-volatile element NV are connected to the electrode of one access transistor MN3 and the output node of the inverter between MP1 and MN1 in the SRAM cell 110, respectively. For the program/erase operations of the non-volatile element NV, it is inevitable that either the source electrodes or the drain electrodes of the non-volatile elements NV need to apply a high voltage bias. In general the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) in SRAM cells are designed for low voltage operations based on the performance and size considerations, and incompatible with the high voltage program/erase operations of non-volatile elements. Thus, the performance and sizes of the SRAM cells 110 in the NVSRAM cells 100 must be comprised. It is also due to the incompatibility of the high/low voltage operations that the gates of MN3 and MN4 are required to form two separated wordlines (wordline 1 and wordline 2 as shown in FIG. 1) in contrast to that of the conventional 6T SRAM, where the gates of MN3 and MN4 form a single wordline. Furthermore, the non-volatile elements with the applied gate voltage below their high threshold voltages are “off” and disconnect the output nodes of MP1/MN1 inverters from the access transistors MN3 connected to bitlines. During the normal SRAM read/write operations a high control gate voltage far higher than the high and low threshold voltages of the non-volatile elements is required to pass the voltages at the output nodes of MP1/MN1 inverters through the access transistors MN3 to bitlines.
To resolve the mentioned issues, we have disclosed the new types of NVMSRAM cell devices for applying one single non-volatile element embedded in the conventional 6T (six-transistor) or 2R4T (two-resistor-four- transistor) SRAM cells.